1. Field of the Invention
The invention relates to the exposure of photo-sensitive layers, particularly photoresist layers, employed in the fabrication of integrated circuits.
2. Prior Art
In the photolithographic fabrication of integrated circuits, photo-sensitive layers, referred to commonly as photoresist layers, are exposed to light which is projected through a masking member or reticle. After the photoresist layer is developed, the patterns defined by the masking member are used to form various circuit elements and regions. Most often the masking member has opaque and transparent areas which result (after the photoresist is developed) into regions of the photoresist material and regions with no such material.
In some applications, it is desirable to have a photoresist layer (after developing) which has regions of different thicknesses. One method of obtaining these regions is to expose the photoresist layer through two different masking members in separate masking steps. This process, however, results in misalignments which are inherent when more than a single masking member is used. The same result is obtained with electron beam masking by having the beam expose some areas more than other areas, although this type of masking is currently more expensive than conventional projection or contact masking.
Related technology to the present invention is disclosed in U.S. Pat. Nos. 4,137,458 and 4,140,913.
As will be seen, the present invention provides a variable thickness, self-aligned photoresist layer with conventional masking techniques. The disclosed process lends itself to cost-efficient, high production processing using masking members which are readily fabricated with current technology.